3/15/72 FPTRAP (III)
NAME fptrap -- PDP-11/45 floating point simulator
SYNOPSIS .globl fptrap
sys ilgins; fptrap
DESCRIPTION fptrap is a package which picks up instructions
which are illegal for the PDP-11/20, and if they
correspond to 11/45 floating point instructions,
simulates their operation. The following in-
structions are supported:
cfcc
setf
seti
setd
setl
clrf fdst
tstf fsrc
absf fdst
negf fdst
mulf fsrc,fr
modf fsrc,fr
addf fsrc,fr
movf fsrc,fr (=ldf)
movf fr,fdst (=stf)
subf fsrc,fr
cmpf fsrc,fr
divf fsrc,fr
movfi fr,dst (=stcfi)
movif src,fr (=ldcif)
movfo fr,fdst (=stcxy)
movof fsrc,fr (=ldcyx)
Here src and dst stand for source and destina-
tion, fsrc and fdst for floating source and des-
tination, and fr for floating register. Notice
that the names of several of the opcodes have
changed. The only strange instruction is movf,
which turns into stf if its source operand is a
floating register, and into ldf if not.
The simulator sets the floating condition codes
on both ldf and stf. The 11/45 hardware does not
set the fcc on stf.
Short and long format for both floating point
numbers and integers is supported. Truncation
mode is always in effect. Traps for overflow and
other arithmetic errors are not supported. Ille-
gal instructions or addresses cause a simulated
trap so that a core image is produced.
The condition code bits are maintained correctly.
For floating-point source operands, immediate
mode ((pc)+) is not supported, since the PDP-
11/45 handbook is not clear on what to do about
it.
After an arithmetic error the result is generally
meaningless.
The arithmetic is always done in double-
precision, so exact but unrounded results are to
be expected in single-precision mode. Double
precision results are probably less correct than
the hardware will be.
The lower parts of the floating registers become
meaningless during single-precision operations.
FILES kept in /usr/lib/liba.a
SEE ALSO PDP-11/45 handbook, ilgins(II)
DIAGNOSTICS trap, c-bit, v-bit
BUGS see above
OWNER ken, dmr